Federal Circuit Report

Philip Eklem

Reichman Jorgensen Lehman & Feldberg LLP

This article discusses the Federal Circuit's opinion in VLSI Technology LLC, v. Intel Corporation ("VLSI")¹ and the case's impact on the Patent Trial and Appeal Board's ability to independently construe disputed claim terms during post-grant proceedings under the America Invents Act. The court held that it was not error for the Board to construe a disputed term based on its own analysis without explicitly adopting or analyzing a district court's prior construction of the same term—which highlights an important aspect of the interplay between district court and PTAB proceedings. The court further held that because there was an active claim construction dispute between the parties, case law restricting Board decisions to arguments raised by the parties does not prohibit the Board from resolving the dispute based on reasoning not proffered by either party.

VLSI and Intel are in the midst of a heated patent dispute that has garnered much attention due to its sprawling nature² and the significant amount of damages at stake.³ Relevant here are VLSI's claims of patent infringement asserted against Intel in the District of Delaware based on U.S. Patent No. 7,247,552 ("the '552 patent").⁴

Intel responded to VLSI's infringement suit by filing three petitions for inter partes review ("IPR") on June 21, 2019, challenging claims 1, 2, 11, and 20 of the '552 patent.⁵ The Board instituted review on all three petitions on February 6, 2020, and subsequently found all challenged claims unpatentable in a single final written decision ("FWD") that covered all three proceedings.⁶ VLSI appealed the Board's decision to the Federal Circuit, principally raising alleged errors of claim construction.⁷

During the IPR proceedings, the Board construed three claim terms: (1) "force region" (recited in claims 1 and 11), (2) "adding dummy metal lines to the plurality of metal-containing interconnect layers" (recited in claim 20), and (3) "being used for electrical interconnection not directly connected to the bond pad" (also recited in claim 20).⁸ Relevant here is the Board's analysis and construction of the "force region" term.

In its June 21, 2019 petition, Intel proposed that "force region" should be construed to mean "a region within the integrated circuit in which forces are exerted on the interconnect structure when a die attach is

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performed."⁹ VLSI's November 8, 2019 Preliminary Response did not propose a construction for that term.¹⁰ Between VLSI's preliminary response and the Board's institution decision, on November 18, 2019, the District of Delaware issued a Markman order adopting a construction of "force region" nearly identical to the construction Intel proposed in its petition: "region within the integrated circuit in which forces are exerted on the interconnect structure when a die attach is performed."¹¹ Nevertheless, in its February 6, 2020 institution decision, the Board "did not provide an express construction for this term but stated that the 'force region' includes at least the area directly under the bond pad."¹²

After institution, VLSI still did not propose a construction of "force region." Instead, VLSI argued that Intel had not shown that the cited prior art teaches a "force region" under Intel's own construction, which requires "a region within the integrated circuit in which forces are exerted on the interconnect structure when a die attach is performed."¹³ VLSI argued that the "die attach" process described in the '552 patent required by Intel's construction corresponds to a "flip chip" bonding process, while the prior art cited by Intel (called "Oda") describes a different type of "wire bonding" process that does not satisfy the "die attach" limitation.¹⁴

In its FWD, the Board did not analyze or address the district court's construction of "force region." Instead, the Board conducted its own claim construction analysis and found "no reason to modify [its] construction of the term 'force region' as including at least the area directly under the bond pad," finding it to be "consistent with the plain language of the claims" and "consistent with the specification," and that "[n]o further construction of this term is required to resolve issues in dispute."¹⁵ The Board determined that the patent describes the "force region" as a region "susceptible to stress from the bond pad due to assembly or other processes," including but not limited to the region underneath a "flip-chip bump pad," a "wire bond pad," or "other packaging or test pad structures."¹⁶ The Board saw "no reason to exclude Oda's wire bonding from the 'assembly or other processes' described in the '552 patent."¹⁷

Accordingly...