In re Intel Corp. Sec. Litig.

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IN RE INTEL CORP. SECURITIES LITIGATION

No. 5:20-cv-05194-EJD

United States District Court, N.D. California, San Jose Division

March 31, 2023

ORDER GRANTING MOTION TO DISMISS WITH LEAVE TO AMEND RE: ECF NO. 56

EDWARD J. DAVILA UNITED STATES DISTRICT JUDGE

Lead Plaintiffs KBC Asset Management NV and SEB Investment Management AB (collectively, “Lead Plaintiffs”) bring this putative class action against Defendants Intel Corporation (“Intel”), former Intel CEO Robert H Swan, Intel CFO George S. Davis,^[1] and former Intel Chief Engineering Officer Dr. Venkata S.M. Renduchintala (collectively, the “Individual Defendants,” and with Intel, “Defendants”), alleging violations of §§ 10(b) and 20(a) of the Securities Exchange Act of 1934 and Rule 10b-5 promulgated thereunder. See Consolidated Compl. (“Compl.”), ECF No. 53. Lead Plaintiffs bring this action individually and on behalf of those who purchased or acquired Intel common stock from October 25, 2019 through October 23, 2020 (the “Class Period”). Id. at 1.

Before the Court is Defendants' motion to dismiss under Federal Rules of Civil Procedure 8(a), 9(b), and 12(b)(6) and the Private Securities Litigation Reform Act of 1995 (“PSLRA”). Mot. to Dismiss (“Mot.”) ECF No. 56, at 1. The Court finds this matter suitable for decision without oral argument. Civil L.R. 7-1(b). Having considered the parties' submissions, the Court GRANTS Defendants' motion to dismiss with leave to amend.

BACKGROUND

I.STATEMENT OF FACTS^[2]

Intel is a semiconductor company that designs and manufactures microprocessors and other semiconductor products for use in computers, data center servers, communications devices, and other digital electronic devices. Compl. ¶ 20, 26. It is headquartered in Santa Clara, California, and its stock trades on NASDAQ under the symbol “INTC.” Id. ¶ 20.

The semiconductor industry is marked by two features relevant to this case. First, semiconductor companies can broadly be characterized as occupying one of two roles: design or fabrication. Id. ¶ 32. Companies that focus only on chip design and marketing employ what is called a “fabless” business model because those companies do not own chipmaking facilities called “fabs.” Id. ¶¶ 29, 32. On the other hand companies that only fabricate chips are called “foundries,” and fabless companies will send their chip designs to foundries to manufacture on their behalf. Id. ¶ 32. Some companies, however perform both design and fabrication functions and are called “integrated device manufacturers,” or “IDMs.” Intel is (mostly) such an IDM. Id. ¶ 29. For its leading-edge chips-those based on the most current, advanced technology-Intel both designs and fabricates the chips in-house. Id. ¶¶ 29, 31. For older, trailing-edge chips and non-Intel designed chips obtained from acquisitions of other companies, Intel outsources some production to foundries. Id. ¶ 31. This business model allows Intel to realize efficiencies by avoiding intermediaries, to coordinate manufacturing capacity with demand, and to better safeguard its intellectual property by keeping its knowledge and expertise in-house. Id. ¶ 30.

The second key feature is that expectations and industry economics are closely tied to an assumption known as Moore's Law, which stems from an observation by Intel co-founder Gordon Moore. In the 1960s, Moore observed that every two years, the number of transistors that could be fabricated in a given area of silicon wafer would double meaning that chips would grow smaller at a rapid rate. Id. ¶ 39. He forecasted that this trend would continue, and history has borne out his prediction. Id. ¶¶ 39, 41. Because development has kept pace with Moore's Law, the semiconductor industry and its analysts now expect chip sizes to shrink in accordance with the cadence of Moore's Law. Id. ¶ 39. The upshot for semiconductor companies is that the first to develop technology for the next smaller chip size-known as a “node,” “process,” or “process node”-gains a significant advantage and can capture a large majority of the revenues for that chip size. Id. ¶ 40. Up through 2011 with the release of its 22nm chip, Intel's chip development had closely followed the progression predicted by Moore's Law, and Intel was a full node ahead of its competitors. Id. ¶ 41.

Although Intel matched the pace of Moore's Law through 2011, it encountered challenges when moving from the 22nm node to the 14nm node. Id. ¶¶ 41-42. Despite planning to begin production of 14nm chips in 2013, Intel was unable to market the chips in large quantities until 2015. Id. ¶ 42. It encountered similar setbacks with the next process node. Id. ¶ 43. Despite the cadence of Moore's Law calling for 10nm chips in 2015, Intel delayed the launch of its 10nm chips to the second half of 2017. Id. Later, it pushed back launch even further into 2019. Id. ¶¶ 43, 45. While Intel dealt with those delays, its competitors began to catch up. By 2018, one of its foundry competitors, TSMC, introduced its 7nm process as Intel continued to work on its 10nm process. Id. ¶ 47. TSMC also formed an alliance with AMD, one of Intel's fabless chip design competitors, allowing AMD to develop increasingly sophisticated chips and seize market share from Intel. Id. ¶¶ 48-51. In an effort to regain ground, Intel hired Jim Keller, a well-regarded microprocessor architect, in April 2018. Id. ¶ 55.

It was against this backdrop of increased competition that Intel began to discuss its upcoming 7nm process with the market. Beginning in May 2019 at an investor meeting, Intel executives, including Swan and Renduchintala, projected that Intel would launch its first 7nm product, known as Ponte Vecchio, in 2021. Id. ¶¶ 60, 62. Renduchintala explained that Intel had learned from the missteps surrounding its 10nm process and that those lessons would allow Intel to meet its anticipated schedule. Id. ¶ 61. Throughout the Class Period, Defendants repeatedly affirmed that Intel's 7nm process was “on track,” reassuring markets that it would meet its 2021 timeline by implementing lessons learned from the 10nm process. Id. ¶¶ 68, 71-72; see also Id. ¶¶ 147, 149, 153, 156, 163, 167, 172, 176, 187.

But, according to Lead Plaintiffs, the 7nm process was not “on track” and had fallen behind schedule while Defendants were making those statements. On December 12, 2019, the technology news website SemiAccurate published an article by Charlie Demerjian reporting that Intel's internal product roadmaps showed some of its 7nm products were already delayed by at least a year. Id. ¶¶ 75, 77; Decl. of Gina F. Elliott (“Elliott Decl.”), ECF No. 57, Ex. 14. A former Senior Director of Marketing at Intel, FE 1, likewise explained, by December 2019, it was understood at Intel that “yea, 7nm is messed up.” Id. ¶ 78. FE 1 also reported that, before December 2019, Intel's former VP of Marketing told FE 1 the 7nm process was one or two years behind schedule. Id. A former Intel Development Technician and Operations Manager, FE 2, noted that Intel was having yield problems with its 7nm process, meaning that too many of the fabricated chips were defective. Id. ¶ 79. Further, according to another SemiAccurate article by Demerjian, on March 31, 2020, Intel missed a hard tapeout deadline for Ponte Vecchio. Id. ¶ 86. Allegedly, the result of missing the deadline was that Intel would be unable to meet its goal of launching Ponte Vecchio in 2021. Id. ¶¶ 84-87. Moreover, leaks of what appeared to be internal Intel slides from May 2020, which were partially in Russian, indicated that some of Intel's other 7nm products were not scheduled to arrive until 2023. Id. ¶¶ 90-91.

FE 1 disclosed that by May or June 2020, Keller, the microprocessor architect hired by Intel in 2018, had come into conflict with Renduchintala over delays to the 7nm process. Id. ¶ 93. Keller purportedly approached Swan to protest what he viewed as Renduchintala's refusal to address problems with development, and he threatened to resign if Swan did not act. Id. When Swan refused Keller's requests, Keller advised the Intel Board of Directors that neither Swan nor Renduchintala should remain in their roles. Id. ¶¶ 93-94. Shortly thereafter, on June 11, 2020, Keller departed Intel due to what were announced as “personal reasons.” Id. ¶ 95. Analysts reacted with concern, writing that Keller's departure “is a big deal and suggests that whatever he was implementing at Intel was not working or the old Intel guard did not want to implement it,” and interpreting the departure as a sign that “Intel's processor and process node roadmaps are going to be more in flux or broken than even we had expected.” Id. ¶ 96. Following the news, Intel's stock price fell by 0.6%, declining from a closing price of $59.70 per share on June 11, 2020, to a closing price of $59.33 per share on June 12, 2020. Id. ¶ 99.

On July 23, 2020, Intel issued a press releasing announcing that its 7nm product schedule would be delayed approximately six months due to problems with yield, and Intel's targets for yield were approximately twelve months behind schedule. Id. ¶ 101. In Intel's Q2 2020 earnings call later that day, Swan also disclosed that Intel would utilize outside manufacturers to make some of its leading-edge 7nm chips and that, for some time, it had been working on contingency plans to allow for its chips to be manufactured by third-party foundries if the need arose. Id. ¶¶ 103-04. Such contingency plans required Intel to design its chips to be made in both Intel and non-Intel fabs an undertaking that would have required eight to twelve months of design work per a former Intel circuit design engineer, FE 3. Id. ¶ 106. Analysts responded negatively to the news, lowering their target prices for Intel and assailing the 7nm delays...