The Trs. of Purdue Univ. v. Wolfspeed, Inc.

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THE TRUSTEES OF PURDUE UNIVERSITY, Plaintiff, v. WOLFSPEED, INC., Defendant.

No. 1:21-cv-840

United States District Court, M.D. North Carolina

March 19, 2024

SUPPLEMENTAL CLAIM CONSTRUCTION MEMORANDUM OPINION AND ORDER

This court has separately addressed claim construction of terms in U.S. Patent No. 7,498,633 (“the ‘633 Patent”). (Doc. 163.) On May 5, 2023, this court held a claim construction hearing with the parties - Plaintiff, the Trustees of Purdue University, and Defendant, Wolfspeed, Inc. - at which time this court took the matter under advisement. (Minute Entry 05/05/2023.) During briefing and the claim construction hearing, Defendant raised a concern about the ‘633 Patent's guidance, or lack thereof, concerning where the JFET region's width is measured. Consequently this court requested, (Doc. 164), and received, (Docs. 167 175 (Plaintiff); Docs. 168, 174 (Defendant)), supplemental briefing on this discrete issue. For the reasons set forth herein, this court will assume without deciding that the claim terms are definite and defer consideration of Defendant's indefiniteness argument as to the below-listed claim terms to a later stage in these proceedings following further findings of fact and expert discovery.

Claim Term

Plaintiff's Construction

Defendant's Construction

“the JFET region having a width less than about three micrometers” (Claim 9)

No construction necessary

Indefinite

“the JFET region having a width of about one micrometer” (Claim 10, depends from Claim 9)

No construction necessary

Indefinite

I. BRIEF OVERVIEW OF THE ‘633 PATENT

At issue here is the ‘633 Patent, entitled “High-Voltage Power Semiconductor Device.” (‘633 Patent (Doc. 83-1) at 2.)^[1] The ‘633 Patent claims particular double-implanted MOSFETS, which - at a high level - act like electric switches allowing or preventing current to flow from an electrode source to a drain. A MOSFET device switches and regulates current in electric circuits by creating static electronic fields in a semiconductor material. (See Ex. 1, Expert Report of W. Allen Doolittle, Ph.D. Concerning Construction of Certain Terms in U.S. Patent No. 7,498,633 (“Doolittle Report”) (Doc. 104-1) at 13.) A vertical MOSFET device consists of several layers: the gate electrode, gate oxide, source electrodes, a series of semiconductor drift layers of differing polarities, and a lower drain layer. (Id. at 14.) Current flows through a channel in the drift layer from the source to the drain. (See id.) Applying a static electric field transverse to the current flow creates a “field effect” that impacts the conductance of a semiconductor device. (See Id. at 13.)

When a MOSFET device is in the on-state, an electric field forms across the oxide layer of the device and permeates into the semiconductor; this creates a channel in which electrons flow from the source region through the drift layer of the device and into the drain terminal. (Id. at 15.) In the off-state, there is a high resistance in the drift layer that blocks voltage applied to the MOSFET device. (See id. at 15-16.) In a MOSFET device, a JFET region is formed from the “pinch[ing] [of] current flow from source to drain . . . .” (Id. at 17.) The pinching action increases the device's resistance. (Id.)

A major “design consideration” in MOSFET devices appears to be balancing a “high blocking voltage” with a low “on-resistance of the semiconductor device” because a decreased on-resistance improves the semiconductor device's efficiency. (‘633 Patent (Doc. 83-1) at 7.) “However, the typical fabrication techniques for reducing the specific on-resistance of high-voltage power semiconductor devices may also reduce the blocking voltage of the device.” (Id.) “One technique to minimize the JFET component on-state resistance involve[s] widening the JFET region and thereby reducing the degree of pinching.” (Doolittle Report (Doc. 104-1) at 18.) However, “[t]hat approach ha[s] drawbacks” because “it increase[s] the cell size of the device” and “compromised] blocking voltage.” (Id.) Relatedly, “a JFET region that [is] too wide would result in the field across the gate oxide in the blocking state to exceed the electric field for oxide breakdown, thus damaging the gate oxide.” (Ex. 2, Expert Report of Stanley Shanfield, Ph.D. (“Shanfield Report”) (Doc. 103-2) at 17.) “[T]he field in the oxide [must] remain below a critical value to avoid early failure of the oxide during operation in the field. . . . [I]n practice[,] the oxide field must be kept below about 3 MV/cm.” (Id.)

“[T]here are a number of well-known design considerations and variables that influence the design of a JFET region.” (Doolittle Report (Doc. 104-1) at 19.) For example, “reducing one component of on-state resistance might increase another,” as “reducing . . . the JFET width might also reduce the channel length and thereby reduce the channel component of on-state resistance,” which “could counteract the increase in JFET resistance.” (Id.)

Blocking voltage and on-resistance appear to be inversely correlated, where both a high blocking voltage and a low on-resistance are desirable. A “JFET region that was too wide would result in the field across the gate oxide in the blocking state to exceed the electric field for oxide breakdown, thus damaging the gate oxide.” (Shanfield Report (Doc. 103-2) at 17.) “On the other hand, a JFET region that was too narrow would increase the on-state resistance, contrary to the design goal” of the MOSFET device. (Id. at 17-18.) “[T]here is an optimum width at which one achieves the lowest on-resistance without allowing the oxide field to exceed the electric field for oxide breakdown in the blocking state.” (Id. at 18.) The ‘633 Patent claims MOSFET devices in which “the JFET region [has] a width less than about three micrometers” and devices in which “the JFET region has a width of about one micrometer.” (‘633 Patent (Doc. 83-1) at 11.)

II. LEGAL STANDARD

In Markman v. Westview Instruments, Inc., 517 U.S. 370 (1996), the Supreme Court clarified which issues in a patent trial are properly reserved for the jury and which are questions of law to be determined by the court. Specifically, the Court held that interpretation of language in patent claims “is an issue for the judge, not the jury[.]” Id. at 391. The Federal Circuit has provided further guidance on how to interpret patent claims, stating that, in general, courts are to give the words of a claim “their ordinary and customary meaning” as understood by “a person of ordinary skill in the art in question at the time of the invention[.]” Phillips v. AWH Corp., 415 F.3d 1303, 1312-13 (Fed. Cir. 2005) (en banc) (citations omitted).

Separate from but related to claim construction is the issue of patent invalidity for indefiniteness. A patent claim is invalid for indefiniteness under 35 U.S.C. § 112 “if [the] claim[], read in light of the specification delineating the patent, and the prosecution history, fail[s] to inform, with reasonable certainty, those skilled in the art about the scope of the invention.” Nautilus, Inc. v. Biosig Instruments, Inc., 572 U.S. 898, 901 (2014). Determining invalidity is a legal question for the court to evaluate. Young v. Lumenis, Inc., 492 F.3d 1336, 1344 (Fed. Cir. 2007) (“A determination that a patent claim is invalid for failing to meet the definiteness requirement in 35 U.S.C. § 112 . . . is a legal question reviewed de novo.”). “The definiteness requirement must take into account the inherent limitations of language, but at the same time, the patent must be precise enough to afford clear notice of what is claimed, thereby apprising the public of what is still open to them.” Fairfield Indus., Inc. v. Wireless Seismic, Inc., No. 4:14-CV-2972, 2015 WL 1034275, at *4 (S.D. Tex. Mar. 10, 2015) (citing Nautilus, 572 U.S. at 907-11). “The definiteness requirement ‘mandates clarity, while recognizing that absolute precision is unattainable.'” Presidio Components, Inc. v. Am. Tech. Ceramics Corp., 875 F.3d 1369, 1375 (Fed. Cir. 2017) (quoting Nautilus, 572 U.S. at 910). Patents are presumed to be valid, and the patent challenger has the burden of proving invalidity by clear and convincing evidence. See Microsoft Corp. v. I4I Ltd. P'ship, 564 U.S. 91, 95 (2011); Takeda Pharm. Co. v. Zydus Pharms. USA, Inc., 743 F.3d 1359, 1366 (Fed. Cir. 2014), cert. denied, 574 U.S. 1026 (2014).

III. ANALYSIS

Defendant argues that the ‘633 Patent fails to specify where the JFET region's width, which varies due to the curvature of the p-well boundaries, should be measured. (Def.'s Opening Claim Construction Br. (Doc. 104) at 23-24; Def.'s Suppl. Claim Construction Br. (Doc. 168) at 4.) Defendant contends that a given MOSFET device may fall within or outside the scope of the ‘633 Patent depending on where the JFET region's width is measured, creating an ambiguity rendering the two claim terms at issue here indefinite. (Def.'s Opening Claim Construction Br. (Doc. 104) at 24, 26; Def.'s Suppl. Claim Construction Br. (Doc. 168) at 5.)

Plaintiff refutes this argument, explaining that “the JFET region should be measured at the narrowest point to achieve the intended design.” (Pl.'s Responsive Claim Construction Br. (Doc. 117) at 9.) Plaintiff contends a person of skill in the art would know there is an optimum width that furthers the MOSFET device's design goal of “achiev[ing] the lowest possible on-resistance while meeting the desired blocking voltage specification.” (Id. (quoting Shanfield Report (Doc. 103-2) at 17-18); see also Pl.'s Suppl. Claim Construction Br. (Doc. 167) at 8 (“[O]nly one optimum width exists at the intersection of these design considerations - the width at the narrowest distance in an operating device”).) In subsequent briefing, Plain...